(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and structure for the creation of interconnect patterns that reduce intermetal capacitance for sub-micron device features.
(2) Description of the Prior Art
In the creation of monolithic integrated circuits numerous interacting electrical device elements are typically created in or on the surface of a semiconductor substrate. Among these device elements are transistors, diodes, bipolar transistors of either NPN or PNP conducting characteristics, Field Effect Transistors of either N or P channel type. After these device elements have been created, these elements must be interconnected in order to form functional semiconductor devices such as analog or digital circuits, flip-flop circuits and memory circuits. From there, the interconnected device elements are further connected to surrounding circuitry, circuit substrates, printed circuit boards and the like.
Semiconductor device performance improvements are typically achieved by a continuing reduction in the dimensions of the device elements. This results in increased device density and increased proximity of device elements that belong to one device or to several, adjacent devices. In order to achieve functional operability of the semiconductor device, none-interactive or interconnected device elements must be insulated from each other. It is well known in the art how to interconnect device elements that reside in or on a single level. As part of the creation of semiconductor devices on one level, these devices are electrically insulated and electrically connected to surrounding electronic components by means of holes that are created in the layer of insulation that surrounds the devices and the device elements. The devices or the device elements are accessed through these holes and further interconnected by (first) conductive interconnecting lines that are created on the surface of a (first) layer of insulating material.
In view of the continuing increase in circuit density, multiple layers of devices or device elements are frequently superimposed over each other by first depositing a second layer of insulating material over the interconnecting lines that have been created on the surface of the first layer of insulation. Holes are created in the second layer of insulation for connections to the first network of interconnecting lines, which can then be followed by creating a (second) network of conductive interconnect lines on the surface of the second layer of insulation. It is clear that this process can be repeated a number of times and is limited not by the nature of the process but by the electrical performance characteristics that are imposed as a consequence of the method of interconnecting semiconductor devices.
It is easy to visualize that, with decreased device dimensions, interconnect lines and networks can quickly deteriorate into very complex structures. This may not be a disadvantage in and of itself but this may, in practical terms, impose severe restrictions on the electrical performance of the assembled package. This limitation becomes even more stringent as the operational frequency of the package increases.
The material of choice for the creation of interconnect lines has for many years been aluminum. While doped polycrystalline silicon can be used for some circuit interconnections, virtually all semiconductor circuits use at least one layer of metal interconnection lines. Such metal interconnection lines are typically formed by depositing a thin film of aluminum or aluminum-copper alloy on the wafer, masking the aluminum layer with resist to define a set of metal interconnection lines, and then anisotropically etching the portions of the metal layer not covered by resist. Reactive ion etching (plasma etching) of metal thin films is usually performed using a plasma in which the wafer is bombarded with ions that react with and remove the exposed regions of metal. Plasma etching is performed in a vacuum chamber, and the etcher""s vacuum pumping system removes most, but not all, of the reaction products. Advantages of plasma ion etching over conventional wet etching processes include the possibilities of process automation, less undercutting of wall profiles and higher packing density.
Copper has in recent times found increased application in the use of metal wires due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper however exhibits the disadvantage of high diffusivity in common insulating materials such as silicon dioxide and oxygen-containing polymers. This leads to, for instance, the diffusion of copper into polyimide during high temperature processing of the polyimide, resulting in severe erosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The erosion may result in loss of adhesion, delamination, voids and ultimately a catastrophic failure of the component. The copper that is used in an interconnect may diffuse into the silicon dioxide layer causing the dielectric to become conductive and also decreasing the dielectric strength of the silicon dioxide layer. A copper diffusion barrier is therefore often required; silicon nitride is often applied as a diffusion barrier to copper. Silicon nitride however has a dielectric constant that is high compared with silicon dioxide thereby limiting the use of silicon nitride in encapsulating copper interconnect lines.
In addition, due to the fact that copper is very difficult to process by RIE, the Chemical Mechanical Polishing (CMP) method may need to be used where copper is used as a wiring material. To polish copper at a high rate without scratching in accordance with the burled wiring formation, the copper etch rate must be raised by increasing the amount of the component responsible for copper etching contained in the polishing slurry. If the component is used in an increased amount, the etching will occur isotropically. Consequently, buried copper is etched away, causing dishing in the wiring. It is, when forming interconnect lines using copper, desirable to use methods that do not depend on patterning the copper lines using a chemical etching process since etching of copper is very difficult and is a process that is only recently being further investigated. The use of copper as a metal for interconnect wiring is further hindered by the susceptibility of copper to oxidation. Conventional photoresist processing cannot be used when copper is to be patterned into various wire shapes. The photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment, such as an oxygen plasma, thereby converting it to an easily removed ash.
The above highlighting of some of the advantages and disadvantages of the use of copper indicates that copper has been receiving a relatively large amount of attention as a material to be used for the creation of conductive interconnects. This to the point where in sub-micron technology copper is extensively used in the fabrication of semiconductor devices. For the vast majority of these applications, interconnect lines are created whereby the cross section of the interconnect lines has a rectangular or square shape. With the sharp decrease in the distance between adjacent copper interconnect lines (the metal pitch), the interconnect lines which typically have a square or rectangular cross section induce high intra-metal parasitic capacitances which is detrimental to optimum device performance, especially for higher frequency device operation. The invention addresses this aspect of creating interconnect lines and provides a method whereby the parasitic intra-line capacitance is reduced.
U.S. Pat. No. 5,109,267 (Koblinger et al.) shows a sloped metallization (See FIG. 5).
U.S. Pat. No. 4,888,087 (Moslehi et al.), U.S. Pat. No. 6,114,243 (Gupta et al.) and U.S. Pat. No. 6,103,619 (Lai et al.) show interconnect shapes and processes.
U.S. Pat. No. 5,821,141 (Huang) shows a capacitor with a rounded top opening.
A principle objective of the invention is to reduce intra-metal parasitic coupling between adjacent interconnecting lines.
Another objective of the invention is to achieve high-performance metal interconnect lines without the use of cost intensive processing steps.
Yet another objective of the invention is to provide a method for the creation of high performance interconnect lines that can readily be integrated into conventional semiconductor manufacturing procedures.
In accordance with the objectives of the invention a new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.